Semiconductor Fabrication

Semiconductor fabrication (or "fab") is the industrial process of manufacturing integrated circuits — the chips that power everything from smartphones to AI accelerators. It involves patterning billions of transistors onto silicon wafers at nanometer scales, and it represents one of the most complex and capital-intensive manufacturing processes ever developed by humanity.

The fabrication process involves hundreds of steps. Silicon wafers are coated with photoresist, exposed to patterned ultraviolet light (photolithography), etched, doped with impurities to create transistors, layered with metal interconnects, and tested — all in ultra-clean environments where a single dust particle can ruin a chip. A leading-edge fabrication facility (fab) costs $20-30 billion to build and takes 3-5 years to bring to full production.

The industry is defined by process nodes, named by feature size (though the numbers are increasingly marketing terms rather than physical measurements). As of early 2026, the leading edge is TSMC's 3nm (N3) process, used in Apple's A17 Pro and M3 chips, with 2nm expected in 2025-2026. Each node generation increases transistor density by roughly 50-70%, enabling either more powerful or more energy-efficient chips. NVIDIA's AI GPUs are fabricated on TSMC's processes: the H100 used 4nm, and the B200 uses TSMC's custom 4NP process.

The geopolitical concentration is striking. TSMC (Taiwan Semiconductor Manufacturing Company) fabricates approximately 90% of the world's most advanced chips. Samsung is the only other company manufacturing at comparable scales. This concentration in Taiwan has made semiconductor fabrication a geopolitical flashpoint, driving massive government investments: the US CHIPS Act ($52 billion), European Chips Act (â43 billion), and similar programs in Japan, South Korea, and India aim to diversify manufacturing geography.

ASML, the Dutch company that produces EUV (Extreme Ultraviolet) lithography machines, holds another critical bottleneck. EUV lithography — required for sub-7nm manufacturing — uses 13.5nm wavelength light generated by vaporizing tin droplets with a laser, focused through complex mirror optics. Each EUV machine costs $350+ million and ASML is the sole supplier. No EUV machines, no leading-edge chips.

For AI specifically, fabrication capacity directly constrains the supply of AI accelerators and HBM. The explosive demand for AI compute has made TSMC's advanced nodes allocation-constrained, with major customers (NVIDIA, Apple, AMD, Qualcomm) competing for wafer starts. This supply constraint is one reason AI infrastructure build-out is measured in years rather than months.

The physics of continued scaling is increasingly challenging. Below 2nm, quantum effects make traditional transistor architectures unreliable. The industry is transitioning to gate-all-around (GAA) transistors, backside power delivery, and eventually stacked (3D) transistor architectures to continue the performance trajectory that AI's computational appetite demands.